1. Technical Field
This invention relates generally to integrated circuit (IC) cell design and, more particularly, to manufacturing approaches for enhanced circuit routing.
2. Related Art
Computer-aided cell-based design has been developed for quickly designing large scale ICs such as application specific integrated circuits (ASICs) and gate arrays. The cell is a circuit that has been pre-designed and pre-verified as a building block. Design technologies known as standard cell and gate array use different types of such building blocks. In a standard cell design, each distinct cell in a library may have unique geometries of active, gate, and metal levels. Examples of a standard cell or gate array cell include an inverter, a NAND gate, a NOR gate, a flip-flop, and other similar logic circuits.
During the process of designing an integrated circuit, a designer may select particular cells from a library of cells and use them in a design. The library includes cells that have been designed for a given IC manufacturing process, such as complementary metal oxide semiconductor (CMOS) fabrication. The cells generally have a fixed height but a variable width, which enables the cells to be placed in rows. Cells typically do not change from one design to the next, but the way in which they are interconnected will, to achieve the desired function in a given design. By being able to select the cells from the library for use in the design, the designer can quickly implement a desired functionality without having to custom design the entire integrated circuit from scratch. Thus, the designer will have a certain level of confidence that the integrated circuit will work as intended when manufactured without having to worry about the details of the individual transistors that make up each cell.
Cells are normally designed so that routing connections between cells can be made as efficiently as possible. Routing in an IC design is accomplished through routing elements, such as wires in one or more metal layers. Each metal layer is separated from other metal layers by insulating layers, and vias connect one metal layer to another. These routing elements perform at least two functions: they connect individual transistors that make up a cell, and they connect cells to each other globally (i.e., on a chip-level) to implement the desired functionality of the integrated circuit. For example, clock signals, reset signals, test signals, and supply voltages may be carried through these routing elements. A well-designed cell layout minimizes congestion in routing global interconnections, which reduces the number of metal layers in or overall size of an integrated circuit layout.
As shown in the prior art standard cell of FIGS. 1-2, a common standard cell architecture will have metal 1 (M1) pins that are primarily on a vertical orientation and connected by horizontal metal 2 (M2) wires. As the cell height is fixed, the available horizontal M2 routing resources to connect each cell are also fixed. Therefore, when no horizontal M2 route resource is available to connect to the M1 pin, a bended M2 wire may be used, as shown in FIG. 2. However, the bended M2 wire is inefficient as it blocks other horizontal M2 tracks. Furthermore, in some current library architectures, an M2 power rail is provided to reduce current density on existing M1 power rails and to improve circuit reliability. Unfortunately, this makes cross-power-rail M2 bending impossible. Therefore, what is needed is a solution to at least this deficiency of the prior art.